The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to an improvement in a method for manufacturing a semiconductor device which has, on a single semiconductor substrate, a bipolar transistor which has a high cutoff frequency and low power consumption, and complementary MOS (CMOS) transistors of a polysilicon gate structure, each of which has high speed switching characteristics and low power consumption.
A semiconductor device having a bipolar transistor and CMOS transistors on a single semiconductor substrate is generally known as a Bi-CMOS. FIG. 1 shows the structure of a conventional Bi-CMOS which is manufactured in the following manner.
First, a p-type silicon substrate 1 is prepared. An n.sup.+ -type buried layer 2 of high impurity concentration is selectively formed in the silicon substrate 1 by diffusion. An n-type epitaxial layer 3 is grown on the entire surface of the silicon substrate 1. A p-type well 5 and a p.sup.+ -type isolation region 4 for electrically isolating each circuit element are formed by thermal diffusion. The annealing time for forming the p-type well 5 is longer than that for forming the p-type isolation region 4. For this reason, the thermal diffusion process for forming the p-type well 5 is partially performed first. Subsequently, the remaining thermal diffusion process for forming the p-type well 5 is simultaneously performed with the thermal diffusion process for forming the p.sup.+ -type isolation region 4. According to the conventional method, a bipolar transistor 6 is formed in a region surrounded by the p-type well 5 and the p.sup.+ -type isolation region 4. A p-channel MOS transistor 8 which is one component of the complementary MOS transistors is formed in a region surrounded by the p-type well 5 and the p.sup.+ -type isolation region 4. An n-type channel MOS transistor 7 which is the other component of the complementary MOS transistors is formed in the p-type well 5.
The conventional method as described above has the following problems. The first problem is undesired migration of an impurity. In the impurity diffusion annealing process for forming the p-type well 5 and the p.sup.+ -type isolation region 4, the n-type impurity of the n.sup.+ -type buried layer 2 migrates upward, so that the impurity concentration of the n-type epitaxial layer 3 cannot be controlled to a predetermined value. In the Bi-CMOS structure shown in FIG. 1, the impurity concentration of the n-type epitaxial layer 3 is directly related to the static characteristics and dielectric strength of the npn bipolar transistor and has a direct influence on a threshold voltage Vth of a p-channel bipolar transistor 8. For this reason, it has been difficult to obtain the desired stable characteristics with the Bi-CMOS structure as shown in FIG. 1 which is manufactured by the conventional method.
The second problem is the difficulty of achieving optimal characteristics of both the bipolar transistors and the CMOS transistors. Thus, it is difficult to obtain a Bi-CMOS structure wherein a bipolar transistor has a high cutoff frequency and low power consumption and CMOS transistors have a high switching speed. The main reasons for the second problem will now be explained with reference to FIG. 1. In the structure shown in FIG. 1, the source and drain regions of the n-channel MOS transistor 7 are formed simultaneously with the emitter region of the npn bipolar transistor 6. Also, the source and drain regions of the p-channel MOS transistor 8 and the base region of the npn bipolar transistor 6 are simultaneously formed. Accordingly, it is difficult to achieve conditions for obtaining optimal characteristics of both the npn transistor 6 and the CMOS transistors. More specifically, in order to obtain the npn bipolar transistor 6 having the desired characteristics, the emitter region must be as shallow as possible. In contrast to this, the source and drain regions of the n-channel MOS transistor 7 which are formed simultaneously with the emitter region of the npn bipolar transistor 6 must have a certain diffusion depth in order to prevent electrode spike (junction destruction due to migration of aluminum) during the manufacture of the aluminum electrode. Thus, the emitter region of the npn bipolar transistor 6 cannot be formed under the optimal conditions for forming the npn bipolar transistor 6. On the other hand, the source and drain of the p-channel MOS transistor 8 which are formed simultaneously with the base region of the npn bipolar transistor 6 are formed deeper than necessary. This restricts miniaturization of the p-channel MOS transistor 8 and causes an increase in the parasitic capacitance, thus impairing the switching characteristics of the CMOS transistors.
A method as shown in FIGS. 2A to 2C is already known as a method for solving the first problem discussed above, as in IBM Technical Disclosure Bulletin Vol. 16, No. 8, pp. 2719 to 2720. According to this method, using a thermal oxide film pattern 12 as a mask formed on a p-type silicon substrate 11, n.sup.+ -type buried layers 13 are formed (FIG. 2A). Subsequently, after removing the thermal oxide film pattern 12, a p-type epitaxial layer 14 is grown. After forming a thermal oxide film 15 on the surface of the p-type epitaxial layer 14, an n-type impurity is ion-implanted through the thermal oxide film 15 so as to form n-type impurity diffusion sources 16 in the surface layer portion of the p-type epitaxial layer 14 on the n.sup.+ -buried layers 13 (FIG. 2B). Then, annealing is performed to slump the diffusion sources 16 so as to form n-type wells 17 which reach to the n.sup.+ -type buried layers 13 (FIG. 2C).
Thereafter, an npn bipolar transistor is formed on one n-type well 17, a p-channel MOS transistor is formed on the other n-type well 17, and an n-channel MOS transistor is formed on the p-type epitaxial layer 14.
According to the method as described above, the upward migration of the impurity from the n.sup.+ -type buried layers 13 caused during formation of the n-type wells 17 shortens the slumping time for forming the n-type wells 17 but does not substantially affect the impurity concentration thereof.
The method shown in FIGS. 2A to 2C can solve the first problem encountered in the manufacture of the Bi-CMCS structure as described above. However, the second problem remains unsolved with this method.